The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device capable of precharging a local input/output (I/O) line to a stable voltage level.
Generally, a plurality of memory banks are designed in a semiconductor memory device such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), and each memory bank is comprised of a plurality of cell arrays. Each cell array comprises cell groups, each of a plurality of memory cells. The memory cell includes a cell transistor and a cell capacitor, and stores one bit of data.
Herein, an area where the memory bank is located is a core cell region, and an area which is formed for inputting/outputting data to/from the memory bank is a peripheral circuit region. The data transferred to the peripheral circuit region through a data input/output (I/O) pin in a write operation of the semiconductor memory device is inputted into the core cell region through a write driver located on a boundary of the core cell region. Generally, a data line coupled to the data I/O pin and the write driver to transfer data is a global input/output (I/O) line GIO, and a plurality of the global I/O lines is called a global input/output (I/O) bus GIO_BUS. The data transferred through the write driver is written in the corresponding memory cell, wherein a data line that is shared with the write driver and each memory cell is called a local input/output (I/O) line LIO.
On the other hand, a precharge operation of the local I/O line LIO is performed as a means to reduce power consumption and increase speed in the semiconductor memory. The precharge operation is performed before the write operation in the semiconductor memory device to bring the local I/O line LIO to a precharging voltage level of a constant voltage level so as to obtain the write operation with higher speed and low power consumption.
FIG. 1 is a block diagram illustrating a partial structure of a conventional semiconductor memory device.
As shown, the conventional semiconductor memory device includes a memory bank 110, a plurality of write drivers 130A and 130B, a plurality of lower precharging units 150A and 150B, and a plurality of upper precharging units 170A and 170B.
The memory bank 110 includes a plurality of cell arrays and sub_hole areas to share a plurality of local I/O lines LIO<0>, /LIO<0>, LIO<1>, and /LIO<1>. Each of write drivers 130A and 130B is connected between a corresponding pair of local I/O lines LIO<0>, /LIO<0> and LIO<1>, /LIO<1>, and a global I/O bus GIO_BUS. Each of lower precharging units 150A and 150B is connected to a corresponding pair of local I/O lines LIO<0>, /LIO<0> and LIO<1>, /LIO<1>. Each of upper precharging units 170A and 170B is located on the other side of the write driver 130A and 130B on the basis of the memory bank 110 and connected to a corresponding pair of local I/O lines LIO<0>, /LIO<0> and LIO<1>, /LIO<1>.
Herein, a plurality of memory cells are provided in the cell array area, and a sense amplifier driver (not shown) is provided in the upper side and the lower side of each cell array area. The sub_hole includes plural circuits sub_hole such as a power source generating unit of the sense amplifier driver (not shown) for generating a power source of the sense amplifier driver corresponding to the cell array, a word line repeater (not shown), and an I/O switch (not shown), etc.
FIG. 2 is a block diagram illustrating a write operation and a precharge operation of the conventional semiconductor memory device.
For the sake of convenience, FIG. 2 shows a partial structure connected to a pair of local I/O lines LIO<0> and /LIO<0> shown in FIG. 1.
With reference to FIG. 2, the simple write operation will be described.
A data input from a global I/O line GIO<0> is applied to a write driver 130A, and the write driver 130A drives the pair of local I/O lines LIO<0> and /LIO<0> to pull up or pull down according to the data applied thereto in response to an enable signal BWEN. Here, the pair of local I/O lines LIO<0> and /LIO<0> comprises a main local I/O line LIO<0> and a sub local I/O line /LIO<0>. For example, the write driver 130A drives the main local I/O line LIO<0> to pull up and the sub local I/O line /LIO<0> to pull down, when the applied data is a logic high level. When the applied data is a logic low level, the write driver 130A drives the main local I/O line LIO<0> to pull down and the sub local I/O line /LIO<0> to pull up.
The data transmitted through the pair of local I/O lines LIO<0> and /LIO<0> is written in the memory cell of the corresponding cell array. The pull up/pull down operation of the main and sub local I/O lines LIO<0> and /LIO<0> is illustrated in FIG. 3.
Subsequently, the precharge operation of the pair of local I/O lines LIO<0> and /LIO<0> before or after the write operation will be described.
First, the lower precharging unit 150A precharges the pair of local I/O lines LIO<0> and /LIO<0> in response to an inverted reset signal RSTB, and the upper precharging unit 170A precharges the pair of local I/O lines LIO<0> and /LIO<0> in response to a reset signal RST. Herein, the inverted reset signal RSTB is generated by inverting the reset signal RST. Further, a signal for precharging the pair of local I/O lines LIO<0> and /LIO<0> such as the reset signal RST and the inverted reset signal RSTB may be changed according to a circuit structure of the lower and upper precharging units 150A and 170A.
For reference, an input/output (I/O) switch 160A includes an n-type metal-oxide semiconductor (NMOS) transistor having a drain-source path connected between the main local I/O line LIO<0> and the sub local I/O line /LIO<0>, and a gate receiving the reset signal RST. In addition, the I/O switch 160A connects the main local I/O line LIO<0> to the sub local I/O line /LIO<0> to equalize voltage levels between two lines in response to the reset signal RST. FIG. 3 illustrates a more detailed write operation, and FIGS. 3 and 4 illustrate the precharge operation.
FIG. 3 is a circuit diagram of the write driver 130A and the lower precharging unit 150A of FIG. 2.
FIG. 3 shows the write driver 130A and the lower precharging unit 150A, wherein the write driver 130A loads data applied on the global I/O line GIO<0> to the pair of local I/O lines LIO<0> and /LIO<0> in response to the enable signal BWEN, and the lower precharging unit 150A precharges the pair of local I/O lines LIO<0> and /LIO<0> to a voltage level of a core voltage VCORE in response to the inverted reset signal RSTB.
In the write operation of the write driver 130A, the inverted reset signal RSTB maintains a logic high level.
If data applied to the global I/O line GIO<0> is a logic high level, a logic low level is latched to a first latching unit LAT1 and the logic high level is latched to a second latching unit LAT2. Thereafter, when the enable signal BWEN is a logic high level, a second driving control signal CTR_DRV2 is a logic low level, thereby to drive the main local I/O line LIO<0> to pull up and the sub local I/O line /LIO<0> to pull down according to the logic levels latched to the first and the second latching units LAT1 and LAT2.
In contrast, if the data applied to the global I/O line GIO<0> is a logic low level, a logic high level is latched to the first latching unit LAT1 and the logic low level is latched to the second latching unit LAT2 so as to drive the main local I/O line LIO<0> to pull down and the sub local I/O line /LIO<0> to pull up. The pair of local I/O lines LIO<0> and /LIO<0> driven to pull up/pull down transmits data to the memory cell of the corresponding cell array.
The lower precharging unit 150A includes first to third PMOS transistors PM1, PM2, and PM3. The first PMOS transistor PM1 has a source-drain path connected between the core voltage VCORE and the main local I/O line LIO<0>, and a gate receiving a signal corresponding to the inverted reset signal RSTB. The second PMOS transistor PM2 includes a source-drain path connected between the core voltage VCORE and the sub local I/O line /LIO<0>, and a gate receiving the signal corresponding to the inverted reset signal RSTB. The third PMOS transistor PM3 includes a source-drain path connected between the main local I/O line LIO<0> and the sub local I/O line /LIO<0>, and a gate receiving the signal corresponding to the inverted reset signal RSTB.
In the precharge operation of the lower precharging unit 150A, if the inverted reset signal RSTB is a logic low level, the first to third PMOS transistors PM1 to PM3 of the lower precharging unit 150A are turned on so that the pair of local I/O lines LIO<0> and /LIO<0> is precharged to the voltage level of the core voltage VCORE. Further, the first to third PMOS transistors PM1 to PM3 equalize the voltage level of the main local I/O line LIO<0> and the sub local I/O line /LIO<0>.
FIG. 4 is a circuit diagram of the upper precharging unit 170A of FIG. 2.
As shown, the upper precharging unit 170A includes first to third PMOS transistors PM4, PM5, and PM6. The first PMOS transistor PM4 includes a source-drain path connected between the core voltage VCORE and the main local I/O line LIO<0> and a gate receiving a signal corresponding to the reset signal RST. The second PMOS transistor PM5 includes a source-drain path connected between the core voltage VCORE and the sub local I/O line /LIO<0> and a gate receiving the signal corresponding to the reset signal RST. The third PMOS transistor PM6 includes a source-drain path connected between the main local I/O line LIO<0> and the sub local I/O line /LIO<0> and a gate receiving the signal corresponding to the reset signal RST.
In the precharge operation of the upper precharging unit 170A, if the reset signal RST is a logic high level, the first to third PMOS transistors PM4 to PM6 of the upper precharging unit 170A are turned on so that the pair of local I/O lines LIO<0> and /LIO<0> is precharged to the voltage level of the core voltage VCORE, and equalize the voltage level of the main local I/O line LIO<0> and the sub local I/O line /LIO<0>.
Referring back to FIG. 1, when the memory bank 110 shares the pair of local I/O lines LIO<0> and /LIO<0>, the precharge operation is performed to the voltage level of the core voltage VCORE in the pair of local I/O lines LIO<0> and /LIO<0> through the lower precharging unit 150A and the upper precharging unit 170A. In order to precharge the pair of local I/O lines LIO<0> and /LIO<0> to the voltage level of the core voltage VCORE more quickly, the lower precharging unit 150A and the upper precharging unit 170A are provided.
In other words, since the pair of local I/O lines LIO<0> and /LIO<0> is very long lines in the semiconductor memory device, when the precharge operation is performed only by one of the lower precharging unit 150A and the upper precharging unit 170A, it takes a long time for all portion of the pair of local I/O lines LIO<0> and /LIO<0> to be up to the voltage level of the core voltage VCORE. If so, operation after the precharge operation may be also delayed.
Consequently, there is a disadvantage of increasing the total operation time of the semiconductor memory device. To solve the problem, the lower precharging unit 150A and the upper precharging unit 170A are provided on both sides of the pair of local I/O lines LIO<0> and /LIO<0> to perform the precharge operation.
However, since a voltage level of an external source voltage VDD is decreased and rapid operation speed of the memory device is desired, it is required that the pair of local I/O lines LIO<0> and /LIO<0> is more stably and quickly precharged up to the desired voltage level.
Furthermore, in the precharging operation of the plurality of pairs of local I/O lines according to the conventional structure, there is a problem that the voltage level of the core voltage VCORE is not stable when the plurality of pairs of local I/O lines are precharged at the same time using the core voltage VCORE.